FPGA Firmware for the Altera EP3C25Q240C8N FPGA written by James Ahlstrom N2ADR The latest firmware is version 1.3
The original firmware was version 1.0.
It still works fine with newer versions of Quisk.
There is no need to upgrade your firmware unless you need the new features.
Note that the firmware version you are using appears on the config screen.
Be sure to set parameter "use_rx_udp" to 1 in your quisk_conf.py for original N2ADR hardware design.
Sources Altera FPGA original hardware "fpga_ver0.zip"
The firmware version 1.1 supports the extra features of the HiQSDR.
Specifically it supports the X1 connector FPGA pins 69, 68, 65, 64 (band in use) ; preamp pin 63;
transmit LED pin 57; the attenuator pins 84, 83, 82, 81, 80; and the antenna switch pin 41.
There is also a new PTT (push to talk) input pin 176 that is used instead of the key input (pin 177) for SSB.
Be sure to use this pin for SSB instead of the key pin if you use the new firmware. This new firmware requires Quisk version 3.5.5 or later.
For the HiQSDR you must set parameter "use_rx_udp" to 2.
Sources Altera FPGA HiQSDR hardware V1.1 "fpga_ver1.zip"
The firmware version 1.2 support for wider transmission bandwidths up to 22 kHz for wider FM and for DRM.
There is also a new "Qs" command that returns the hardware status as the same string used by the "St" command.
There is no need to upgrade unless you need to transmit FM, or you wish to query the hardware with the "Qs" command (for example by Hamlib).
Sources Altera FPGA HiQSDR hardware V1.2 "fpga_ver2.zip"
The firmware version 1.3 fixes a problem with spectrum flatness when sampling at 960 ksps, and adds the special features used by the Quisk VNA program. The VNA program "quisk_vna.py" enables the hardware to be used as a vector network analyzer, and it requires this firmware or above.
Sources Altera FPGA HiQSDR hardware V1.3 "fpga_ver3.zip"
The firmware version 1.4 allows you to change the IP address of the hardware from the PC instead of using the address programmed into the firmware. It also changes FPGA pin 56 to be an output pin; high for normal, and low for full duplex (FDX) operation.
Sources Altera FPGA HiQSDR hardware V1.4 "fpga_ver4.zip"
The Firmware for the Altera FPGA are written from James Ahlstrom N2ADR with the programming language Verilog and the Altera Quartus II Web Edition. (~2Gb)
FPGA Alternative Sources
FPGA Firmware for HiQSDR written by Stefan DL2STG. Stefan has made a extension to the original FPGA Software written by James to access the raw data from the ADC and also added a new 16K*14Bit RAM.
Now the HiQSDR can also be used as a wideband spectroscope or as oscilloscope.
This FPGA image is fullly compatible with version 1.3 of James N2ADR.
Access to the raw RAM data is independent of the other functions, so the spectroscope and quisk can run in parallel.
FPGA/HiQScope Hompage of Stefan DL2STG
FPGA Additional Information
For more information about the Altera Cyclone III FPGA, please refer to:
Altera Cyclone III Handbook or
Altera Documentation: Cyclone III Devices
Additional Pin Information for the Cyclone III EP3C25 Device is available at Pin Information for the Cyclone II EP3C25
To change the FPGA Software, an adapter to the Altera interface on the pcb is necessary.
Altera USB-Blaster, EEBlaster or similar devices. The adapter should be able to work in AS-Mode Active Serial Programming.
The pinout of the 10pin micromatch connector X4 are 1:1 compatible to the original Altera USB-Blaster or EEBlaster.
|Comparison table AS-Mode PS-Mode JTAG|
|PIN 4||Vtarget +3.3V||Vtarget +3.3V||Vtarget +3.3V|
Note: Mode of Programming should be Active Serial Programming and the Device are EPCS16 the flash chip.
For more iformation about programming, please refer to chapter 9. "Configuration, Design Security, and Remote System Upgrades" in the Altera Cyclone III Handbook.
A good and cheap JTAG / AS Mode Interface which works with the Altera FPGA and Quartus is EEBlaster from the Austrian company Entner Electronics http://www.entner-electronics.com/tl/index.php/eeblaster.html
Special note: Sergey Kuzmin RV3APM wrote a good description about the firmware update.
The latest version from Sergey is available in the file section RV3APM of the n2adr-sdr yahoo-group. (Login required)
A copy of Sergey's document is contained in this media under the following link. Firmware Update HiQSDR
Network Address and Ports
HiQSDR FPGA hardcoded static IP-Address: 192.168.2.196
With Firmware version 1.4 from James Ahlstrom N2ADR it is possible to send a different IP address to your HiQSDR, this helps to solve network address range problems.
HiQSDR FPGA standard UDP Ports:
- UDP 0xBC77: Receive Port (48247) send receive I/Q data to the LAN
- UDP 0xBC78: Control Port (48248) send and receive control data (Frequency and Mode)
- UDP 0xBC79: Transmit Port (48249) receive I/Q data from the LAN
Note: The standard IP-Adress of the HiQSDR is hardcoded in the FPGA software.
If you need to change the IP-Adress of your HiQSDR edit the file ethernet.v at the FPGA sources, then compile and upload the new Code to your HiQSDR.
To run more than one HiQSDR on the same network you have to change every HiQSDR to his own IP and MAC address at the FPGA sources.
Also be shure that your Router, Computer and the HiQSDR are in the same Class A network section 192.168.2.X , if needed change the settings from your router to this Class A network range.
Normally all new network cards detect the HiQSDR automatically, but if you have problems to ping your HiQSDR, try it with a crossover network cable.
Controlling the N2ADR fully digital frontend
Mario Roessler DH5YM wrote a document about controlling the N2ADR fully digital frontend HiQSDR.
This document describes the control strategy, the interfaces and the control frame format.
The latest version from Mario is available in the file section DH5YM's folder of the n2adr-sdr yahoo-group. (Login required)
A copy of Mario's document is contained in this media under the following link. Controlling the N2ADR full digital frontend
This document are also aviable in the German language. Ansteuerung des N2ADR/HiQSDR DDC/DUC Frontends (FW V1.1)