HiQSDR-Information

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Concept from James Ahlstrom N2ADR

James Ahlstrom N2ADR developed a digital direct conversion DDC transceiver based on a 14bit ADC converter from Analog Devices which is connected to an Altera Cyclone III FPGA.
The FPGA decimates/interpolates and filters the signals and transfers the data to a 100BaseT Ethernet controller; all data needed is sent via UDP to and from the programmed IP-Adress in your local network.

The ARRL QEX magazine of January/February 2011 featured an article An All-Digital Transceiver for HF by James Ahlstrom which describes his approach for designing a software-defined HF transceiver.

You will find this article in PDF file format via the following link:
http://www.arrl.org/files/file/QEX_Next_Issue/Jan-Feb_2011/QEX_1_11_Ahlstrom.pdf

Helmut Goebkes DB1CC used this concept as a base to construct a modern multilayer SMD-PCB, with some functional improvements as a base module of complete DDC/DUC transceiver.

Refer to the block diagramm:
BlockDiagram.png

Some Facts:

HiQSDR specification
Frequency range 30 kHz - 62 MHz (with oversampling up to several hundred Mhz)
Operation modes RX/TX CW, SSB, AM, FM digital modes, depending on Software
Bandwidth switchable 48 kHz - 960 kHz
Attenuator -0..42 dB switchable in -2 dB steps
Transmit Power MMIC 0..17 dBm = 1..50 mW
Voltage 6 - 7 V
Current 850 - 950 mA
Network datarate 46.08 megabit/sec at 960 kHz bandwidth


  • A 10/100 full duplex Ethernet controller and its RJ-11 jack.
    All communication is over UDP packets on Ethernet.
    The FPGA program supports Ping, ARP, Tx samples, Rx samples, tuning and status.
  • A analog to digital converter (ADC) (14 Bit) and its preamp for receive.
  • A digital to analog converter (DAC) (14 Bit) for transmit.
  • Another 8-bit DAC to control the transmit output level.
  • A extreme low jitter (-162dBc/1MHz) 122.88 MHz clock as master frequency oscillator.
  • The FPGA is an Altera EP3C25Q240C8N, 240 pins, programmed by an EPCS16SI8N holds RX and TX parts simultaneously to allow full duplex operation.
  • The Ethernet controller is a LAN9115, and runs full duplex at 10 or 100 mbps.
  • The Ethernet jack is a Stewart SI-50170-F, Digikey part number 380-1103-ND.
  • The clock is a Crystek 122.88 MHz CVHD-950-122.880
  • The receive ADC is a 125 MHz 14-bit Texas Instruments ADS5500IPAP in 64-TQFP.
  • The ADC preamp is a Linear Technology LTC6405.
  • The transmit DAC is an Analog Devices 14-bit AD9744.
  • The transmit level control DAC is an Analog Devices AD7801.
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